The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device which has MIS (Metal-Insulator-Semiconductor) gate type structure.
A power metal-oxide semiconductor field effect transistor is one of the semiconductor devices which have MIS gate type structure. The demand of the power metal-oxide semiconductor field effect transistor as a switching element, for example, in the circuit for charge and discharge of a lithium ion battery etc. is increasing sharply. The power metal-oxide semiconductor field effect transistor is required to have a high breakdown voltage in a power use, and further, it is needed to have a lower ON resistance in order to control electric power loss. Especially, in the case where the power metal-oxide semiconductor field effect transistor is used for a battery drive type portable device etc., it is an urgent requirement to lower the power consumption of the circuit by lowering the ON resistance.
FIG. 24 is a schematic section view showing the element structure of the principal part of DT (Deep Trench) type power metal-oxide semiconductor field effect transistor (hereafter, abbreviated as “DTMOS”), as, for example, disclosed by Japanese Patent Laid-Open Publication No, 2002-170955. That is, DTMOS 10 has a structure where n-type pillar regions 12 and p-type pillar regions 14 are provided in parallel on an n++ type silicon substrate 11. And trenches 16 filled up with insulators are provided adjoining these n-types pillar regions. Depths D of the trenches 16 are about 60 micrometers, for example. And, a width W of the n-type pillar region 12 and the p-type pillar region 14 sandwiched between a pair of the trenches 16, is about 10 micrometers, for example.
FIG. 25 is a schematic diagram illustrating a plane arrangement of the trenches 16. A size L of one side of a chip DTMOS 10 is about 5 mm. By providing the trenches 16 in parallel and adjoining as illustrated in FIG. 25, it becomes possible to raise the current density of an element and to carry out switching of large current.
In FIG. 24 again, a p-type base region 20 is provided in a planar fashion on the p-type pillar region 14. And, a p+ type base region 22 is provided in a planar fashion on the surface of the p-type base region 20. Furthermore, n+ type source regions 24 are provided in the ends of the surface of the p+ type base region 22.
The regions from the n-type pillar regions 12 to the n+ type source regions 24 through the p-type base regions 20 are covered with the gate insulating films 30, and the gate electrodes 32 are laminated on the gate insulating films 30. Moreover, the circumferences and the upper surfaces of the gate electrodes 32 are protected by the insulating interlayer films.
The n-type pillar regions 12 are the paths of the main current which flows through the element by applying ON voltage to the gate electrodes 32. Therefore, ON resistance can be lowered by making impurities concentrations of the n-type pillar regions 12 high. On the other hand, the breakdown voltage of the element can be maintained by the depletion layers extended in a transverse direction from the p-n junctions between the n-type pillar regions 12 and the p-type pillar regions 14, and the trenches 16 embedded by the insulator. That is, by providing the trenches 16 filled up with the insulator, the widths of the n-type pillar regions 12 and the p-type pillar regions 14 can be narrowed, and the n-type pillar regions 12 and the p-type pillar regions 14 can be depleted completely. Consequently, the current paths of the element of the depleted regions and the current paths of the element of the insulated regions can be intercepted completely, and a high breakdown voltage can be realized. That is, DTMOS illustrated in FIG. 24 is power metal-oxide semiconductor field effect transistor compatible with the fall of ON resistance and the rise of the breakdown voltage.
However, as a result of an examination by the Inventors of the present invention, it turned out that it is desirable to give a peculiar feature in the lead-outing structure of wirings in the case where the semiconductor device provided such DTMOS in its package is manufactured from a viewpoint of reliability and a manufacture yield.